Dr. Peter Andrew Jamieson — Academic in an information evolution

Projects & Games

What’s newest is up top; the CAD/FPGA research tools and smaller builds are below.

FPGA CAD & Research Software

Odin II

An open-source Verilog HDL synthesis tool for CAD research — simpler to build and run than the original Odin, on any modern *NIX system.

VPR 5.0 Power Models

Updated power models for VPR 5.0 covering the newer architecture file format and uni-/bi-directional routing.

Superseded by VTR — go there for the current power models and full CAD flow.

Verilog-to-Routing (VTR)

The current academic FPGA CAD flow — the successor to VPR and Odin, and where their power/placement/routing work continues.

verilogTown

An educational Verilog/FPGA game, built as a professor, that teaches HDL design through play. Its own site.

GroundHog

A benchmark suite built with Nokia for evaluating FPGAs and reconfigurable architectures in the mobile domain.

GA-lapagos

A genetic-algorithm research codebase (GitHub) supporting several of the GA papers and student projects.

Fun & Small Builds

Fish Fun — Population Simulation

A Processing-built population simulator — big and little fish, breeding, eating, and the emergent behaviour that falls out of a few simple rules.

Pomodoro Timer

A hand-drawn (crayon!) kitchen timer built in Processing for trying out the Pomodoro Technique.