Project Name: Accelerating GAs on FPGA with a framework ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ Project Area: GAs, FPGA, Domain Specific Languages ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ Target: Not sure yet ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ People Needs and Allocation: Ph.D. worthy topic ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ Skills: Programming, Hardware Design, Compiler? ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ Description: The FPGA is a good computational device for bit level manipulations, and GAs, potentially are bit level applications for them to run. This is particularly true for our chromosome GA for combinatorial optimization. For this reason, it is an interesting question to solve if a framework can be designed and then mapped onto an FPGA, FPGA/CPU, or other bit-strong computation space to accelerate these algorithms. Questions of interest? 1. Is the FPGA or similar acceleration substrates good for these types of problems? 2. Is there a way to generalize the design process either through domain specific languages (DSL) or frameworks (similar to Ruby on Rails) that would allow easy mapping and efficient use of these devices? 3. What aspects of the GA are best for acceleration? Note that GAs are inherently parallel as each individual is distinct from the others. 4. Can we use the FPGA for early death of off-spring in a high fecundity, low viability approach? 5. Is the FPGA equally good at bit chromosomes, combinatorial chromosomes, and our new chromosome as an acceleration vehicle? 6. Accelerating the Xover on FPGAs could be a paper on it's own ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ References: - Parallel genetic algorithms on multiple fpgas. L Guo, AI Funie, DB Thomas, H Fu, W Luk - A General Framework for Accelerating Swarm Intelligence Algorithms on FPGAs, GPUs and Multi-Core CPUs D Li, L Huang, K Wang, W Pang, Y Zhou - High-performance parallel implementation of genetic algorithm on fpga MF Torquato, MAC Fernandes - Selected aspects and tradeoffs in transistor level implementation of genetic algorithms S Jeżewski, R Długosz - A fully customizable hardware implementation for general purpose genetic algorithms M Peker ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------ Resources: